1. Technical Field
The present invention relates to a semiconductor test device, semiconductor test circuit connection device, and semiconductor test method that enable various kinds of semiconductor device test to be integrally carried out, and relates in particular to a rationalization of a power semiconductor module test method, an improvement of testing conditions (waveform), and a semiconductor test device improved thereby.
2. Related Art
Final tests and various kinds of test during the manufacturing process on power semiconductor products typified by an insulated gate bipolar transistor (IGBT), a power metal oxide semiconductor field effect transistor (MOSFET), or the like, are broadly divided into a thermal resistance test, a DC parametric test, and an AC parametric test. As test circuits normally used for each of these tests differ, independent semiconductor test devices are used.
A thermal resistance test of a power semiconductor product is a test for measuring the heat release characteristics of a package, and guaranteeing the quality thereof. Also, in a DC parametric test, static characteristics such as a semiconductor element leakage current or on-voltage are measured. Herein, the DC parametric test may also be called a DC parameter characteristic test, a static characteristic test or, using the name of a characteristic configuring a DC characteristic, a breakdown voltage, leak current, forward voltage test, gate threshold voltage value test, or the like. A DC tester with which it is possible to test the DC characteristics collectively, or a DC/thermal resistance tester that also includes a thermal resistance test function, also exist for the purpose of a semiconductor element DC parametric test, and it is customary to carry out the Final tests and in-process tests using one of these testers.
Meanwhile, an AC parametric test of a power semiconductor product is a test for measuring switching characteristics, or the like, typified by the fall time when a semiconductor element carries out a switching action, the reverse recovery time of a high speed diode (FWD: free wheeling diode) incorporated in the semiconductor element, or the like, and guaranteeing the quality thereof. In the case of the AC parametric test too, it may be called a dynamic characteristic test, or by the name of a test for measuring an individual AC characteristic. For example, it may be a switching characteristic test, a load short circuit test, a short circuit safe operation area (SCSOA) test, a reverse bias safe operation area (RBSOA) test, an avalanche test, or a reverse recovery characteristic test. Of the AC parametric tests, the switching test (turn off test and reverse bias safe operation area test) and FWD reverse recovery characteristic test can, in principle, be implemented with a common test circuit, and an integrated test device is generally used for both tests. However, as a circuit different from the switching test circuit is necessary for the load short circuit test and SCSOA test, the tests are carried out using an independent load short circuit tester.
In this way, when shipping a power semiconductor product, it is common to carry out the tests using in the region of four testers, a DC tester, a thermal resistance tester (or a DC/thermal resistance integrated tester), a switching tester, and a load short circuit tester.
Hereafter, a description will be given, based on FIGS. 17 to 22, of an outline of heretofore known testers for a power semiconductor module.
FIG. 17 is a circuit diagram showing a configuration of a heretofore known test circuit for a switching test. Herein, a test circuit used in a switching test for a 6-in-1 module used when driving a three-phase alternating current motor is shown. FIG. 18 is a timing chart showing an example of measurement signals supplied to the test circuit of FIG. 17. A heretofore known testing procedure for a device under test is also shown in JP-A-2009-229259.
With this test circuit, it is possible to test, for example, a 6-in-1 type IGBT module 1 formed of six IGBTs as a device under test (DUT). A DC power source 3 is connected between a P terminal and N terminal of the IGBT module 1 across a protective switch circuit 2. Also, an electrolytic capacitor 4 with a largish capacity is normally connected in parallel with the DC power source 3 in order to supply a charge sufficient to be able to carry a specified current from the DC power source 3, which is a power source unit. Gate drive units 51 are individually connected to the gate and auxiliary emitter terminal (gate drive emitter terminal) of the IGBT of the switch circuit 2 and each of U to Z phase IGBTs. An inductor 6 is connected as a load in a star connection to a U terminal, V terminal, and W terminal for IGBT module 1 output.
In the timing chart shown in FIG. 18, a two-pulse gate signal is continuously applied to each phase. This is in order to carry out a turn off characteristic (switching characteristic) or RBSOA test when the IGBT is turned off, and carry out a reverse recovery characteristic test on the FWD of the opposing arm (for example, the X-phase FWD when switching the U-phase) simultaneously with carrying out an IGBT turn on characteristic test when the IGBT is turned on. When surge voltage occurring due to circuit inductance when turning off exceeds the DUT withstand voltage, suppression of the surge voltage may be achieved by connecting a snubber circuit between the P terminal and N terminal, or between the collector and emitter of the IGBT phase under test, as necessary (refer to Fuji Electric Systems Co., Ltd. “Fuji IGBT Module Application Manual” (pages 5-8 to 5-14), [online], February, 2010, [searched for on Sep. 17, 2010], internet URL:http://www.fujielectric.co.jp/products/semiconductor/technical/application/index.html).
Also, although the inductor 6, which is the load, is connected to the output terminals in a star connection in FIG. 17, it may also be connected in a delta connection. Also, it is also possible to use a chopper circuit for the switching test and reverse recovery characteristic test. In a combination of two IGBTs, one upper and one lower (for example, the combinations of the U and X phases, V and Y phases, and W and Z phases of the DUT of FIG. 17), with the load inductor 6 connected between the collector and emitter of the IGBT on the side of the arm opposing the phase for which the switching test is carried out (for example, when carrying out the switching test on the X phase IGBT, the opposing arm thereof is the U phase), an on-pulse (generally +15V in the case of an N-channel IGBT) is applied to the gate electrode of the IGBT phase (herein, the X phase) for which the switching test is carried out, the gate pulse is reduced to 0V or less when a specified current is reached, and the current is shut off. At this point, an X phase IGBT turn off characteristic or RBSOA test is carried out. Next, when applying an on-pulse to the gate electrode of the X phase IGBT again while the current previously shut off by the X phase IGBT is flowing back through the circuit of the load inductor 6 and opposing arm (U phase) FWD, the IGBT is turned on, but this time the X phase IGBT turn on characteristics and U phase FWD, which is the opposing arm, reverse recovery characteristics are tested (refer to Fuji Electric Systems Co., Ltd. “Fuji IGBT Module Application Manual” (pages 2-5 to 2-6), [online], February, 2010, [searched for on Sep. 17, 2010], internet URL:http://www.fujielectric.co.jp/products/semiconductor/technical/application/index.html).
FIG. 19 is a circuit diagram showing a configuration of a heretofore known test circuit for a load short circuit test. FIG. 20 is a timing chart showing an example of switch signals and phase gate signals in the test circuit of FIG. 19. Herein, a load short circuit test is a test whereby, in a condition in which a DUT such as an IGBT or power MOSFET is connected directly (with no load) to a DC power source, an on-signal is applied for a specified period to the DUT, and the presence or otherwise of DUT damage is confirmed during that period (refer to Fuji Electric Systems Co., Ltd. “Fuji IGBT Module Application Manual” page 5-2, [online], February, 2010, [searched for on Sep. 17, 2010], internet URL:http://www.fujielectric.co.jp/products/semiconductor/technical/application/index.html).
Changeover switches SW1 to SW5 for connecting a power source directly to the IGBT of a phase under test included in an IGBT module 1 are included in the test circuit of FIG. 19. Herein, switching between the switches SW1 to SW5 is carried out according to a specified procedure, and an on-pulse is supplied for a specified period to the gate of the IGBT of the phase under test. By so doing, a large current of 100 A to 10,000 A or more is carried for a time of a few microseconds to a few tens of microseconds between the collector and emitter electrodes of the IGBT module 1.
In the load short circuit test, generally, by causing a large current to flow for a short period through the IGBT module 1, the voltage between the collector and emitter electrodes, or between the gate and emitter electrodes, of the DUT is greatly affected by the test circuit inductance while the current change is occurring. For this reason, it is necessary to configure main circuit wiring, such as wiring connecting the electrolytic capacitor 4, which is the DC power source, and the collector and emitter electrodes of the DUT, and wiring causing the output terminals of FIG. 19 to mutually short circuit, to be extremely short in accordance with the DUT switching speed, energy to be applied, and the like. For example, it is preferable to reduce the length to 50 nH or less in the case of an IGBT module 1 through which a short circuit current of 3,000 A or more flows, to 100 nH or less in the case of 1,000 A or more, and to 200 nH or less in the case of 500 A or more. Also, in the event of a particular request, the test current value or turn off time may be measured, cross-checked with a standard value, and evaluated as good or defective.
However, in the heretofore known test circuit, it is necessary to select switches that can carry a large current as the switches SW1 to SW5, and to connect them with short wiring. For this reason, when a large amount of space in a test device is taken up by the switch mechanism, it is difficult to dispose components, such as the inductor, required in the switching test circuit of FIG. 17. Therefore, it is common that an independent tester is used for each of the load short circuit test and switching test.
Also, here too, in the same way as in the switching test circuit of FIG. 17, the electrolytic capacitor 4 is disposed in parallel with the DC power source 3 or, when it is necessary to suppress surge voltage, a snubber circuit is connected.
FIG. 21 is a circuit diagram showing an example of a heretofore known DC parametric test device test circuit.
A DC power source, a constant current source, a measurement circuit, changeover switches thereof, and the like, are incorporated in a main body of a DC tester 7, and various types of DC characteristic can be measured. For a DC parametric test on a type wherein a plurality of IGBTs and FWDs are incorporated in one DUT package, for example, the IGBT module 1, it is common to insert a switcher 8 (also called a scanner) between the DC tester 7 and IGBT module 1. The switcher 8 is a device incorporating a plurality of switches, and has a function of automatically connecting each terminal of the IGBT and FWD of the phase to be measured to the input terminals of the DC tester 7. When the DUT is a 1-in-1 module with one semiconductor element, each terminal may be directly connected to the corresponding input terminal of the DC tester 7, and the DC characteristics measured.
Herein, the DC tester 7 may have three input terminals—a gate terminal G, collector terminal C, and emitter terminal E corresponding to the names of the DUT terminals—or four input terminals—the gate terminal G, the collector terminal C, a main circuit emitter terminal E1, and a gate drive auxiliary emitter terminal E2. When it is necessary to increase the measurement accuracy, a Kelvin connection is used. In this case, the switcher 8 and each terminal are connected by two lines, a force line F and a sense line S. For a thermal resistance test too, the configurations of the DC tester 7 and switcher 8 are the same as in the case of the DC parametric test device.
Of the heretofore known test circuit configurations, it is necessary to connect an electrolytic capacitor, snubber circuit, test inductor, and the like, to the DUT for the switching test shown in FIG. 17 and the like, meaning that, as they have an effect on the DC characteristic measurement shown in FIG. 21, it is not possible to use the same contact device. Because of this, it is necessary that the switching test, and DC parametric test and thermal resistance test, are carried out with independent testers and contact units.
FIG. 22 is a plan view showing a circuit wiring structure in the test circuits of FIGS. 17 and 19. The load inductor and short circuit test changeover switches SW1 to SW5 connected to the output terminals U, V, and W of the IGBT module are not shown.
A circuit wiring structure configured of a copper pattern corresponding to the circuit wiring portion surrounded by a broken line 10a of FIG. 17 is shown in FIG. 22. A copper plate 11 configures a positive electrode side copper pattern, and is disposed between the DC power source 3 and protective switch circuit 2. One end of a copper wire 3a, of which the other end is connected to the positive side of the DC power source 3, is screwed down by the positive electrode terminal portion of the electrolytic capacitor to a terminal portion 11a of the copper plate 11. The switch circuit 2 is configured of, for example, an IGBT, and includes the gate terminal G, main circuit emitter terminal E1, gate drive auxiliary emitter terminal E2, and collector terminal C. A copper bar 12 connects the copper plate 11 and switch circuit 2, one end being screwed down to a terminal portion 11d, and the other end to the collector terminal C of the switch circuit 2.
A gate drive unit 52 is connected by wire to the gate terminal G and auxiliary emitter terminal E2 of the switch circuit 2, and furthermore, is also connected to a control unit 5. The emitter terminal E1 of the switch circuit 2 is connected via a copper bar 13 to an IGBT module 1P terminal contact portion 1P by the copper bar 13 being screwed down. A copper bar 14 is connected between an IGBT module 1N terminal contact portion 1N and a terminal portion 15d of a copper plate 15 configuring a negative electrode side copper pattern by being screwed down. The copper plate 15 is disposed in a condition in which it is approximately superimposed on the copper plate 11 across an unshown insulating body, and one end of a copper wire 3b, of which the other end is connected to the negative side of the DC power source 3, is screwed down by the negative electrode terminal portion of the electrolytic capacitor to a terminal portion 15c of the copper plate 15. The electrolytic capacitor 4 shown in FIG. 17, and the like, is connected to the two copper plates 11 and 15 by terminal portions 11a and 15a, terminal portions 11b and 15b, and terminal portions 11c and 15c. Although the electrolytic capacitor shown in FIG. 17 has a three capacitor parallel connection specification, there is no particular limitation to three capacitors, and the quantity of capacitors connected in parallel or series is determined in accordance with the charge needed for the test, which is determined by test current, voltage, and circuit inductance.
Also, a snubber circuit 9 and surge voltage protection diode 2d are disposed in positions between the copper bars 13 and 14 connected to the IGBT module 1 contact portions 1P and 1N. The snubber circuit 9 and surge voltage protection diode 2d are connected by screwing down to the copper bars 13 and 14 via copper bars 13a and 13b and copper bars 14a and 14b respectively.
The copper plate 11 and copper bar 12, the copper plate 15 and copper bar 14, and the copper bars 13, 13a, and 13b, may each be configured integrally (as one copper plate), without being connected by screwing down.
The wiring method shown in FIG. 22 is easily changed, and can accommodate a variety of DUTs. That is, there is an advantage in that, simply by preparing wiring members such as the copper plates 11 and 15 and copper bars 12 to 14, which have a plurality of pattern forms, it is possible to configure a test circuit with a comparatively high degree of freedom.
On the other hand, however, as the wiring in the test circuit as a whole is long, surge voltage (overvoltage) caused by wiring inductance when the DUT is turned off is liable to occur. Also, the current when the DUT is turned on rises while being limited by the test voltage and wiring inductance, and the current change rate (di/dt) becomes gentler. For this reason, a problem occurs in that measurement of characteristics such as rise time (tr) becomes difficult, or stress applied in an FWD reverse recovery test is insufficient. Naturally, to counter these problems, a snubber circuit (refer to Fuji Electric Systems Co., Ltd. “Fuji IGBT Module Application Manual” (pages 5-8 to 5-14), [online], February, 2010, [searched for on Sep. 17, 2010], internet URL: http://www.fujielectric.co.jp/products/semiconductor/technical/application/index.html) has been connected heretofore with the object of absorbing a voltage surge when turning off. Also, a method such as connecting a comparatively large capacitor in a close position between the P terminal and N terminal of the DUT has also been employed in order to steepen the di/dt when turning on.
However, even in the same AC parametric test, it is necessary to dispose all of a load inductance, a changeover switch thereof, terminal short circuit changeover switches, an electrolytic capacitor, and a snubber circuit in the immediate vicinity of the DUT in order to reduce the stray inductance of the test circuit. This is because the stray inductance is a cause of surge voltage occurring during the test, and of the current change rate (di/dt), which is one test condition, becoming gentler, and causes a problem such as the voltage and current oscillating, damaging the DUT.
However, with this method of dealing with the matter, there are problems in that the quantity of each part increases, current measurement becomes complicated because it is necessary to cancel the current flowing through the snubber circuit in order to measure only the current flowing through the DUT, and the like. Moreover, when the DUT is damaged, the whole of the charge stored in the capacitor connected to the P and N contact portions of the DUT flows from the capacitor into the DUT. Because of this, when the capacity of the capacitor disposed in the immediate vicinity is large, the sound of explosion when the DUT is damaged is large, and there is a problem in that the state of damage to not only the DUT but also the peripheral circuit portion is noticeable. Therefore, with the exception of limited semiconductor test devices that have a low capacity range IGBT as a DUT, the switching test of FIG. 17, and the like, and the load short circuit test of FIG. 19, and the like, have heretofore each been implemented with an independent tester.
In this way, when implementing an AC parametric test (switching test), AC parametric test (load short circuit test), thermal resistance test, and DC parametric test sequentially, heretofore, an independent tester and test contact device have been necessary for each test, and it has not been possible to use the same components or measurement circuits in each tester. Because of this, the initial investment when introducing a semiconductor test device, that is, the equipment cost, increases. Also, as the DUT needs to be loaded into and unloaded from a plurality of test contact devices, and moreover, time is needed to switch a mechanical switch, testing efficiency decreases, and personnel costs for implementing the tests also increase. Furthermore, there is a problem such as that a conveying unit when conveying the DUT to the semiconductor test device is also complicated and expensive.